DK-DEV-5SGXEA7N【PDF 164/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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6-8

Emulated LVDS Buffers in Stratix V Devices

SV51007

2014.01.10

Emulated LVDS Buffers in Stratix V Devices

The Stratix V device family supports emulated LVDS on all I/O banks:

? You can use unutilized true LVDS input channels as emulated LVDS output buffers (eTX), which use

two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS, and

RSDS I/O standards.

? The emulated differential output buffers support tri-state capability.

High-Speed I/O Design Guidelines for Stratix V Devices

There are several considerations that require your attention to ensure the success of your designs. Unless

noted otherwise, these design guidelines apply to all variants of this device family.

PLLs and Clocking for Stratix V Devices

To generate the parallel clocks ( rx_outclock and tx_outclock ) and high-speed clocks ( diffioclk ), the

Stratix V devices provide fractional PLLs in the high-speed differential I/O receiver and transmitter channels.

Related Information

? SERDES and DPA Bank Locations in Stratix V Devices on page 6-2

Provides information about the PLL locations available for each Stratix V device.

? Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only on page 6-8

? Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-8

Guideline: Use PLLs in Integer PLL Mode for LVDS

To drive the LVDS channels, you must use the PLLs in integer PLL mode. The center or corner PLLs can

drive the LVDS receiver and transmitter channels.

However, the clock tree network cannot cross over to different I/O regions. For example, the top left corner

PLL cannot cross over to drive the LVDS receiver and transmitter channels on the top right I/O bank.

Related Information

Pin Placement Guidelines for DPA Differential Channels on page 6-13

Provides more information about the fractional PLL clocking restrictions.

Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only

The high-speed clock generated from the PLL is intended to clock the LVDS SERDES circuitry only. Do not

use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted

by the PLL F OUT specification.

For more information about the F OUT specification, refer to the device datasheet.

Related Information

Stratix V Device Datasheet

Altera Corporation

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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